Gate Level Optimisation of Primitive Operator Digital Filters using a Carry Save Decomposition

This paper introduces a method for optimising digital filter realisations at the gate level. The method is based on a derivative of the primitive operator approach of Bull and Horrocks which is extended using a cany-save decomposition of the primitive operator graph. This facilitates the generation of a set of boolean expressions for the multiply-accumulate section of the filter which can be minimised using standard sum of products or Reed Muller techniques. The technique is fully described and results are presented for a representative range of FIR filters. Savings of up to 83% are obtained for sum-of-products minimisation when compared to a CSD coded hard-wired multiplier solution. Initial results suggest further improvements in excess of 20% for the Reed Muller case INTRODUCTION The efficient (multiplier-free) realisation of fixed transfer function digital filters has been the focus of much research in recent years, particularly for applications such as video signal processing where high throughput and low silicon cost are dominant design constraints. The primirive operator filter (POF) methodology [ 11 embodies one technique for reducing implementation complexity by exploiting the redundancy inherent in a multiplier-based realisation. It does this by replacing all inner product multiplication operations by a single directed signal flow graph, employing only primitive operations (additions, subtractions and power of two gains). The graph is formed in a way which preserves the specified filter transfer function, with no loss of coefficient accuracy. The design process has been automated in the form of a package, POFGEN [2], and has been shown to offer significant savings in real applications (eg[3]). This paper discusses a derivative of the above technique which facilitates further decomposition 'of the POF graph, using a curry-save approach, into a form amenable to boolean minimisation. This in turn, allows the system to be realised efficiently in either a sum of products or Reed Muller form [4]. This methodology was introduced in basic form in reference [4], but it is only recently that design tools have become available [2] which facilitate the full evaluation of its potential. The approach yields benefits in the following ways: 0 inexpensive and flexible technologies such as PLAs and FPGAs can be used for implementation, 0 the need for pipeline registers and hence the overall latency of the filter can be significantly reduced, 0 gate counts are reduced especially if PLA based methods are employed, 0 the irregular communication structure of the POF graph is easily mapped onto a regular array structures amenable to VLSI realisation, 0 bit-parallel and bit-serial arithmetic methodologies are supported, and control overheads are reduced for bit-serial designs. The paper begins with an introduction to the decomposition technique and includes an illustrative example. It continues by presenting results for both sum-of-products and Reed Muller synthesis methods, indicating the savings possible for a range of FIR filters. THE CARRY-SAVE DECOMPOSITION In the simple addition-only POF graph [l], vertices represent two-input adders and edge gains are constrained to values of zero or unity. A sub-graph is illustrated in figure 1, where the output signal from any vertex, k, is represented by Wk[n] and where the carry signal, Ck[n], propagates within the vertex. This propagation occurs in time for a bit-serial system and space for a bit-parallel system. If the carry signal is unfolded and propagated to an adjacent vertex in a replicated version of the original sub-graph, figure 2, then, provided that all sub-graph outputs are accumulated correctly, the graph transfer function is preserved. This form of decomposition can be applied iteratively to all vertices in the original and replica graphs allowing each vertex input output relationship to be described in terms of two simple Authorized licensed use limited to: UNIVERSITY OF BRISTOL. Downloaded on February 9, 2009 at 10:25 from IEEE Xplore. Restrictions apply. Figure 1 Primitive operator sub graph boolean expressions. Decomposing all vertices in this manner facilitates minimisation of the entire graph using standard boolean techniques. In general, if the sum output at a vertex, k, in precedence level, p , of the graph is given by Wp,k[n] and the associated carry by C k[n], then the general boolean expressions for a full adder f at level p are given by equations (1) and (2). Clearly if p=O, then the carry in, C-l,k[n] = 0, and hence all vertices at this level represent half adders. All vertices in the graph can thus be represented in the form of (1) and (2). At each successive level of decomposition, all signals associated with the top precedence level in the preceding sub-graph are eliminated. Hence the process terminates after all precedence levels in the graph have been fully decomposed. This results in a structure comprising D sub-graph sections with decreasing complexity. An upper bound on D is given by: 1 i l i i Figure 2 Single vertex decomposition Where Amax is the maximum number of precedence levels in the original POF graph. If edge gains in the original POF graph are allowed to assume any value in {2i}, Amax can be significantly reduced. Shifts can be accommodated in the decomposition process by allowing sum paths to propagate across sub-graph boundaries in the same manner as the carry paths. The number of subgraphs, D, is now a function of the graph edge gains as well as the number of precedence levels and the upper bound is now given by: An added advantage in this case is that many vertices within the carry-save graph have a simpler form and the resulting boolean expressions are more amenable to reduction. This technique is illustrated by the example in figure 3 for the case of the a simple FIR filter coefficient set { 1,2,3,6}. The boolean equations for this example are given below: woo = x02 WOI = xoo WO2 = woo w03' wOl 63 w02 = wOI w02